Recently, there have been numerous attempts to utilize stress in order to improve the performance of CMOS field effect transistor (FET) devices. Uniaxial stress can be introduced by various techniques. Among them, the use of a stressed nitride film deposited over a polysilicon (polySi) gate structure has been widely adopted. Such a technique for introducing stress into the channel regions of FETs is reported, for example, in A. Shimizu et al. “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, 2001 IEEE IEDM Tech. Digest, pp. 433-436; Shinya Ito et al. “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, 2000 IEEE IEDM Tech. Digest, pp. 247-250; and F. Ootsuka et al. “A Highly Dense, High-Performance 130 nm Node CMOS Technology for Large Scale System-on-a-Chip Applications”, 2000, IEEE IEDM Tech. Digest, pp. 575-578.
However, on conventional (100) semiconductor wafers, two kinds of stressed liners are needed in order to improve both the electron and hole mobility at the same time, namely, the use of a tensile stressed liner for nFETs and the use of a compressively stressed liner for pFETs. See, for example, H. S. Yang et al. “Dual Stress Liner for High Performance sub-45 nm Gate Length SOI CMOS Manufacturing”, IEEE IEDM 2004 Tech. Digest, pp. 1075-1077. Thus, use of two different types of stressed liners adds to the complexity of the process and requires an additional mask, thus rendering processing of such CMOS devices more costly and making it more difficult to obtain a high production yield.
In addition, stressed shallow trench isolation (STI) tends to induce stress (compressive, in most cases) in the device channels. On (100) wafers, transverse compressive stress increases the electron mobility, while it decreases the hole mobility. Hence, the narrow-width effect is opposite for nFETs and pFETs.
Despite the advances made in fabricating semiconductor structures with enhanced carrier mobility, there is still a continued need for providing new and improved semiconductor structures having enhanced carrier mobility, which overcome the drawbacks mentioned herein above.